bitkeeper revision 1.1494 (428e647cwMGQpFEvYX5LZ0S3SXAZVQ)
authorkaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk>
Fri, 20 May 2005 22:28:12 +0000 (22:28 +0000)
committerkaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk>
Fri, 20 May 2005 22:28:12 +0000 (22:28 +0000)
Read VMX configuration details from architectural registers.
Signed-off-by: Nitin Kamble <nitin.a.kamble@intel.com>
Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
xen/arch/x86/vmx.c
xen/arch/x86/vmx_vmcs.c
xen/include/asm-x86/msr.h
xen/include/asm-x86/vmx_vmcs.h

index 6b296bb8e95585a6c323bb0df5096365ee0deac2..fecc98f7911235e9d4f721fa970c08e2e877c5e0 100644 (file)
@@ -51,10 +51,10 @@ void do_nmi(struct cpu_user_regs *, unsigned long);
 int start_vmx()
 {
     struct vmcs_struct *vmcs;
-    unsigned long ecx;
+    u32 ecx;
+    u32 eax, edx;
     u64 phys_vmcs;      /* debugging */
 
-    vmcs_size = VMCS_SIZE;
     /*
      * Xen does not fill x86_capability words except 0.
      */
@@ -63,6 +63,18 @@ int start_vmx()
 
     if (!(test_bit(X86_FEATURE_VMXE, &boot_cpu_data.x86_capability)))
         return 0;
+    rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx);
+
+    if (eax & IA32_FEATURE_CONTROL_MSR_LOCK) {
+        if ((eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) == 0x0) {
+                printk("VMX disabled by Feature Control MSR.\n");
+               return 0;
+        }
+    }
+    else 
+        wrmsr(IA32_FEATURE_CONTROL_MSR, 
+              IA32_FEATURE_CONTROL_MSR_LOCK | IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0);
 
     set_in_cr4(X86_CR4_VMXE);   /* Enable VMXE */
 
index b4906bf9050c3232432ba02ff2303b06262ebdab..e840c4c3d0de4a4c06aa5e85d75f933c6a8bb26b 100644 (file)
 struct vmcs_struct *alloc_vmcs(void) 
 {
     struct vmcs_struct *vmcs;
-    unsigned int cpu_sig = cpuid_eax(0x00000001);
+    u32 vmx_msr_low, vmx_msr_high;
 
+    rdmsr(MSR_IA32_VMX_BASIC_MSR, vmx_msr_low, vmx_msr_high);
+    vmcs_size = vmx_msr_high & 0x1fff;
     vmcs = (struct vmcs_struct *) alloc_xenheap_pages(get_order(vmcs_size)); 
     memset((char *) vmcs, 0, vmcs_size); /* don't remove this */
 
-    vmcs->vmcs_revision_id = (cpu_sig > 0xf41)? 3 : 1;
+    vmcs->vmcs_revision_id = vmx_msr_low;
     return vmcs;
 } 
 
index 5eeda436a79e7998f1c7efcdc5ab280f2185b229..e576613c1338142f6a8edae69f1bdd0da470b58b 100644 (file)
 #define MSR_IA32_PLATFORM_ID           0x17
 #define MSR_IA32_EBL_CR_POWERON                0x2a
 
+/* MSRs & bits used for VMX enabling */
+#define MSR_IA32_VMX_BASIC_MSR                  0x480
+#define IA32_FEATURE_CONTROL_MSR                0x3a
+#define IA32_FEATURE_CONTROL_MSR_LOCK           0x1
+#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON   0x4
+
 /* AMD/K8 specific MSRs */ 
 #define MSR_EFER 0xc0000080            /* extended feature register */
 #define MSR_STAR 0xc0000081            /* legacy mode SYSCALL target */
index 1a39bb7a02495b7741129020a7b3f64d1a032d8f..5fe27f002e71766fba8888ffcdb21cebdab5bf4e 100644 (file)
@@ -31,7 +31,6 @@ void vmx_enter_scheduler(void);
 
 #define VMX_CPU_STATE_PG_ENABLED        0       
 #define        VMX_CPU_STATE_ASSIST_ENABLED    1
-#define VMCS_SIZE                       0x1000
 
 struct vmcs_struct {
     u32 vmcs_revision_id;